The Introduction to QFN Package

Ⅰ. What is QFN Package?

QFN (Quad Flat No-leads Package), one of the surface-mount packages. It is worth noting that the  QFN  package is completely different from the LCC  package,  The LCC  still has extension pins, but the pins are bent to the bottom, while the QFN package does not have any extension pins at all.  QFN is the name prescribed by the Japan Electronic Machinery Industry Association.

The four sides of the package are equipped with electrode contacts. Because there are no leads, the mounting area is smaller than  QFP  and the height is lower than QFP. However, when stress is generated between the printed circuit board and the package.  it cannot be relieved at the electrode contact. Therefore, the number of electrode contacts is difficult to achieve as many  QFP pins, generally from 14 to 100. There are two kinds of materials: ceramic and plastic. When there is an LCC  mark, it is basically ceramic QFN. The electrode contact center distance is 1.27mm. Plastic QFN is a low-cost package of glass epoxy printed substrate. In addition to 1.27mm, there are two types of electrode contact center distance: 0.65mm and 0.5mm. This kind of package is also called plastic LCC.  PCLC, P-LCC, etc.

Ⅱ. The Features of QFN Package

QFN is a leadless package with a square or rectangular shape. There is a large exposed pad at the center of the bottom of the package for heat conduction, and there are conductive pads around the periphery of the package for electrical connection. Since the QFN  package does not have gull-wing leads like the traditional SOIC and TSOP packages, the conductive path between the internal pin and the pad is short, the self-inductance and the wiring resistance in the package are very low, so it can provide excellent electrical performance. In addition, it also provides excellent heat dissipation performance through the exposed lead frame pad, which has a direct heat dissipation channel to release the heat in the package,  Usually, the heat dissipation pad is directly soldered on the circuit board, and the heat dissipation vias in the PCB  help to diffuse the excess power consumption into the copper ground plane, thereby absorbing the excess heat.

The QFN package with exposed thermal pads, due to its small size, lightweight, and outstanding electrical and thermal properties, this package is particularly suitable for any application that requires size, weight, and performance. We compare the 32-pin QFN with the traditional 28-pin PLCC package,  The area (5mm×5mm) is reduced by 84%, the thickness (0.9mm) is reduced by 80%, and the weight (0.06g) is reduced by 95%. The parasitic effect of electronic packaging has also increased by 50%, so it is very suitable for high-density printed circuit boards for mobile phones, digital cameras, PDAs, and other portable small electronic devices. Standards or follow the process standards (such as  IPC -SM-782) to carry out. Since QFN is a brand-new package type, industry standards or guidelines for printed board pad design have not yet been formulated. Moreover, after the pad design is completed, some tests are needed to verify it. Of course, in the case of full consideration of various other factors such as the thermal pad at the bottom of the component, the tolerances of the pins, and the package.  the design principles can still be formulated with reference to the  IPC method.

QFN's pad design mainly has three aspects: ① the pad design of the peripheral pins; ② the design of the middle thermal pad and via; ③ the consideration of the structure of the PCB solder mask.

Via design

The QFN package has excellent thermal performance, mainly due to the large-area heat dissipation pad at the bottom of the package,  In order to effectively conduct heat from the chip to the PCB. The bottom of the PCB must be designed with corresponding heat dissipation pads and heat dissipation vias. The heat-dissipating pad provides a reliable soldering area, and the vias provide a way to dissipate heat.

Usually, the size of the thermal pad is at least matched with the exposed pad of the component. However, various other factors need to be considered, such as avoiding bridging with surrounding pads. Therefore, the size of the thermal pad needs to be revised. See Table 1 for specific dimensions. The number and size of the heat dissipation vias depend on the application of the package.  the power of the chip and the electrical performance requirements. It is recommended that the spacing of the heat dissipation vias is 1.0mm～1.2mm, and the size of the vias is 0.3mm～0.33mm. There are four design forms for heat dissipation vias: such as using a dry film solder mask to resist solder from the top or bottom of the via; or using liquid photosensitive (LPI) solder mask to fill from the bottom; or using "through holes". These methods are described in Figure 4. All of these methods have advantages and disadvantages: solder mask from the top is better for controlling the generation of air holes, but the solder mask on the top surface of the PCB  will hinder the solder paste printing; and the bottom barrier and underfill are due to The escape of gas will produce large pores, covering 2 thermal vias, which has an adverse effect on thermal performance; through-holes allow the solder to flow into the vias, reducing the size of the pores, but the solder on the pads on the bottom of the component Will decrease. The design of the heat dissipation vias should be determined according to the specific situation, and it is recommended to use the solder mask form.

The reflow curve and peak temperature also have a great influence on the formation of pores. After many experiments, it has been found that in the underfilled thermal pad area, when the peak reflow temperature increases from 210°C to 215°C to 220°C, the pores decrease; For through holes, the solder outflow at the bottom of the PCB  decreases with the decrease of the reflow temperature.

It is recommended to use an NSMD solder mask. The solder mask opening should be 120μm～150μm larger than the pad opening, that is, the gap between the pad copper foil and the solder mask layer is 60μm～75μm. This allows the solder mask to have a manufacturing tolerance, usually this tolerance is Between 50μm and 65μm, when the lead pitch is less than 0.5mm, the solder mask between the leads can be omitted.

Stencil design

Whether to get perfect and reliable solder joints, printing screen design is the key first step. There is a direct relationship between the opening size of the surrounding pad screen and the thickness of the screen. Generally, thicker screens can be designed with an opening size slightly smaller than the pad size, while the opening size of thinner screens can be designed to be 1:1. It is recommended to use a laser to make a mesh plate with openings and electropolishing.

(1) The stencil design of the surrounding pads

The thickness of the stencil determines the amount of solder paste printed on the PCB,  Too much solder paste will cause bridging during reflow soldering. Therefore, it is recommended that the 0.5mm pitch QFN package use a 0.12mm thickness stencil, and the 0.65mm pitch QFN package uses a 0.15mm thickness stencil. It is recommended that the stencil opening size should be appropriately smaller than the pad to reduce the occurrence of solder bridging. , As shown in Figure 5.

(2) The stencil design of the thermal pad

When the exposed pads on the bottom of the chip are soldered to the thermal pads on the PCB.  the gas in the thermal vias and large-size pads will escape outward, resulting in a certain amount of gas holes. If the solder paste area is too large, it will Various defects (such as sputtering, solder balls, etc.) are produced, but it is almost impossible to eliminate these pores, only to reduce the pores to a minimum. Therefore, when designing the stencil in the thermal pad area, carefully consider it. It is recommended to open multiple small openings in this area instead of one large opening. The typical value is 50% to 80% of the solder paste coverage, as shown in the figure. 5 shown. The practice has proved that the thickness of the solder joint of 50μm is very helpful to improve the board-level reliability. In order to achieve this thickness, it is recommended that the thickness of the solder paste for the underfill thermal via design should be at least 50%; for the through-hole, the coverage rate should be at least Above 75%.

Ⅲ. QFN Solder Joint Inspection and Repairment

(1) Inspection of solder joints

Since the solder joints of QFN are under the package body and the thickness is relatively thin, X-ray can not detect the low tin and open circuit of QFN solder joints, and can only rely on the external solder joints to judge as much as possible, but currently related to QFN soldering The standard for determining partial defects on the side surface has not yet appeared in the IPC standard. In the absence of more methods, for the time being, we will rely more on the testing stations in the later stages of production to judge the quality of welding.

(2) Repairment

For QFN rework, because the solder joints are completely at the bottom of the component package.  any defects such as bridges, open circuits, solder balls, etc. need to be removed, so it is somewhat similar to  BGA  rework. QFNs are small in size, light in weight, and they are used on high-density assembly boards, making them more difficult to repair than BGA. At present, QFN rework is still an urgent development and improvement part of the entire surface mount process. In particular, solder paste must be used to form a reliable electrical and mechanical connection between the QFN and the printed board. There are indeed some difficulties. There are currently three feasible methods for applying solder paste: one is the traditional small screen printing solder paste on the PCB, the other is to spot solder paste on the pads of the high-density assembly board; the third is to print the solder paste directly On the component's pad. The above methods require very skilled repair workers to complete this task. The selection of rework equipment is also very important. For QFN, it is necessary to have a very good welding effect, and it is necessary to prevent the components from being blown off due to too much hot air.The PCB  pad design of QFN should follow the general principles of IPC. The design of the thermal pad is the key. It plays a role in heat conduction. Do not cover it with a solder mask, but the design of the via is best to resist. When designing the stencil of the thermal pad, it must be considered that the amount of solder paste released is within the range of 50% to 80%. How much is appropriate? It is related to the solder mask of the through-hole. The through-hole during soldering is inevitable, so adjust it well. The temperature curve minimizes the pores. QFN package is a new type of package,  We need to do more in-depth research in terms of PCB  design, process, inspection, and repair.

The QFN package (quad flat no-lead package) has good electrical and thermal properties, is small in size, and is light in weight. Its application is growing rapidly. The QFN package using a miniature lead frame is called an MLF package (micro lead frame). The QFN package is somewhat similar to the  CSP  (chip size package), but there are no solder balls on the bottom of the component. The electrical and mechanical connection with the   PCB   is achieved by printing solder paste on the  PCB pads and soldering joints formed by reflow soldering.